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| DS2482-100 Single-Channel 1-Wire Master www.maxim-ic.com GENERAL DESCRIPTION The DS2482-100 is an ICa to 1-WireO bridge device that interfaces directly to standard (100kHz max) or fast (400kHz max) IC masters to perform bidirectional protocol conversion between the IC master and any downstream 1-Wire slave devices. Relative to any attached 1-Wire slave device, the DS2482-100 is a 1-Wire master. Internal factory trimmed timers relieve the system host processor from generating time-critical 1-Wire waveforms, supporting both standard and Overdrive 1-Wire communication speeds. To optimize 1-Wire waveform generation, the DS2482-100 performs slew rate control on rising and falling 1-Wire edges and provides additional programmable features to match drive characteristics to the 1-Wire slave environment. Programmable strong pullup features support 1-Wire power delivery to 1-Wire devices such as EEPROMs and sensors. The DS2482-100 combines these features with an output to control an external MOSFET for enhanced strong pullup application. The IC slave address assignment is controlled by two binary address inputs, resolving potential conflicts with other IC slave devices in the system. FEATURES IC Host Interface, Supports 100kHz and 400kHz IC Communication Speeds 1-Wire Master IO with Selectable Active or Passive 1-Wire Pullup Provides Reset/Presence, 8-Bit, Single-Bit, and Three-Bit 1-Wire IO Sequences Standard and Overdrive 1-Wire Communication Speeds Slew Controlled 1-Wire Edges Selectable 1-Wire Slave Presence-Pulse Falling Edge Masking to Control Fast Edges on the 1-Wire Line Supports Low-Impedance 1-Wire Strong Pullup for EEPROMs, Temp Sensors, or Other 1-Wire Slaves that have Momentary High Current Modes 2 Address Inputs for IC Address Assignment Wide Operating Range: 2.9V to 5.5V, -40C to +85C 8-Pin, 150-mil SO Package ORDERING INFORMATION PART DS2482S-100 DS2482S-100/T&R TEMP RANGE -40 to +85C -40 to +85C PIN-PACKAGE 8 SO (150 mil) 8 SO (150 mil) APPLICATIONS Printers Medical Instruments Industrial Sensors Cell Phones, PDAs TYPICAL OPERATING CIRCUIT VCC *RP (IC port) SDA SCL PCTLZ Optional circuitry Current Limiting Resistor PIN CONFIGURATION VCC IO GND SCL 1-Wire Device 1 2 3 4 8 7 6 5 AD0 AD1 PCTLZ SDA C DS2482-100 AD0 AD1 *Rt 1-Wire line IO 1-Wire Device 1-Wire Device I2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 1-Wire is a Registered Trademark of Dallas Semiconductor. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 21 REV: 110204 DS2482-100: Single-Channel 1-Wire Master ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Maximum Current into Any Pin Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature -0.5V, +6V 20mA -40C to +85C +150C -55C to +125C See IPC/JEDEC J-STD-020A Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. ELECTRICAL CHARACTERISTICS (VCC = 2.9V to 5.5V, TA = -40C to +85C.) PARAMETER Supply Voltage Operating Current 1-Wire Input High 1-Wire Input Low 1-Wire Weak Pullup Resistor 1-Wire Output Low Active Pullup On Time Strong Pullup Voltage Drop 3.3V Pulldown Slew Rate (Note 6) 5V Pulldown Slew Rate (Note 6) 3.3V Pullup Slew Rate (Note 6) 5V Pullup Slew Rate (Note 6) Power-On Reset Trip Point SYMBOL VCC ICC VIH1 VIL1 RWPU VOL1 tAPUOT DVSTRPU CONDITIONS 3.3V 5V (Note 1) 3.3V (Notes 2, 3) 5V (Notes 2, 3) 3.3V (Notes 2, 3) 5V (Notes 2, 3) (Note 4) At 4mA load Standard (Notes 4, 5) Overdrive (Notes 4, 5) VCC 3.2V, 1.5mA load VCC 5.2V, 3mA load Standard (3.3V 10%) Overdrive (3.3V 10%) Standard (5.0V 10%) Overdrive (5.0V 10%) Standard (3.3V 10%) Overdrive (3.3V 10%) Standard (5.0V 10%) Overdrive (5.0V 10%) MIN 2.9 4.5 1.9 3.4 TYP 3.3 5.0 MAX 3.7 5.5 0.75 UNITS V mA V 0.75 1.0 800 2.3 0.4 2.5 0.5 1675 0.4 2.7 0.6 0.3 0.5 1 5 2 10 0.8 2.7 1.3 3.4 4.2 22.1 6.5 40 4 20 6 31 2.2 V W V s V V/s V/s V/s V/s V PDSRC PDSRC PUSRC PUSRC VPOR 1-Wire Timing (Note 5). See Figures 3, 5, 6, and 7. Write 1/Read Low Time Read Sample Time 1-Wire Time Slot Fall Time High-to-Low at Standard Speed (Note 6) Fall Time High-to-Low at Overdrive Speed (Note 6) tW1L tMSR tslot Standard Overdrive Standard Overdrive Standard Overdrive 3.3V to 0V (Note 7) 5.0V to 0V (Note 7) 3.3V to 0V (Note 7) 5.0V to 0V (Note 7) 2 of 21 7.6 0.9 13.3 1.4 65.8 9.9 0.54 0.55 0.10 0.09 8 1 14 1.5 69.3 10.5 8.4 1.1 15 1.8 72.8 11.0 3.0 2.2 0.59 0.44 s s s tF1 s DS2482-100: Single-Channel 1-Wire Master PARAMETER Write-0 Low Time Write-0 Recovery Time Reset Low Time Presence Detect Sample Time Sampling for Short and Interrupt Reset High Time Presence-Pulse Mask Start Presence-Pulse Mask Stop Control Pin (PCTLZ) Output-Low Voltage Output-High Voltage IC Pins (Note 9) See Figure 10 LOW Level Input Voltage HIGH Level Input Voltage Hysteresis of Schmitt Trigger Inputs LOW Level Output Voltage at 3mA Sink Current Output Fall Time from VIhmin to VILmax with a Bus Capacitance from 10pF to 400pF Pulse Width of Spikes that are Suppressed by the Input Filter Input Current Each I/O Pin with an Input Voltage Between 0.1VCCmax and 0.9VCCmax Input Capacitance SCL Clock Frequency Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Set-Up Time for STOP Condition VIL VIH Vhys VOL tof tSP Ii Ci fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO 3 of 21 (Notes 12, 13) (Note 14) SDA and SCL pins only (Notes 10, 11) (Note 10) 0 0.6 1.3 0.6 0.6 0.9 250 0.6 -10 60 VCC = 2.9V to 3.7V VCC = 4.5V to 5.5V 0.7 x VCC 0.05 x VCC -0.5 0.25 x VCC 0.22 x VCC VCC + 0.5V V V V 0.4 250 50 10 10 400 V ns ns A pF kHz s s s s s ns s SYMBOL tW0L tREC0 tRSTL tMSP tSI tRSTH tppm1 tppm2 VOLP VOHP CONDITIONS Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive (Note 8) (Note 8) VCC = 2.9V, 1.2mA load current 0.4mA load current VCC - 0.5V MIN 60 7.1 5.0 2.8 570 68.4 66.5 7.1 7.6 0.7 554.8 70.3 9.5 57 TYP 64 7.5 5.3 3.0 600 72 70 7.5 8 0.75 584 74 10 60 MAX 68 7.9 5.6 3.2 630 75.6 73.5 7.9 8.4 0.8 613.2 77.7 10.5 63 0.4 UNITS s s s s s s s s V V DS2482-100: Single-Channel 1-Wire Master PARAMETER Bus Free Time Between a STOP and START Condition Capacitive Load for Each Bus Line Oscillator Warm-Up Time Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: SYMBOL tBUF Cb tOSCWUP CONDITIONS MIN 1.3 TYP MAX UNITS s (Note 15) (Note 16) 400 100 pF s Note 15: Note 16: Operating current with 1-Wire write byte sequence followed by continuous Read of Status register at 400kHz in Overdrive. With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on threshold VIL1 may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not exceed 300pF. Active pullup guaranteed to turn on between VIL1MAX and VIH1MIN. Active or resistive pullup choice is configurable. Except for tF1, all 1-Wire timing specifications and tAPUOT are derived from the same timing circuit. Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in the same direction and by the same degree. These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew rate is slightly faster. Fall time high-to-low (tF1) is derived from PDSRC, referenced from 0.9 x VCC to 0.1 x VCC. Presence-pulse masking only applies to standard speed. All IC timing values are referred to VIHmin and VILmax levels. Applies to SDA, SCL, and AD0, AD1. I/O pins of the DS2482 do not obstruct the SDA and SCL lines if VCC is switched off. The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. A fast-mode IC-bus device can be used in a standard-mode IC-bus system, but the requirement tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode IC-bus specification) before the SCL line is released. CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times according to IC-bus Specification v2.1 are allowed. IC communication should not take place for the max tOSCWUP time following a power-on reset. PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 NAME VCC IO GND SCL SDA PCTLZ AD1 AD0 FUNCTION Power Supply Input IO Driver for 1-Wire Line Ground Reference IC Serial Clock Input. Must be tied to VCC through a pullup resistor. IC Serial Data Input/Output. Must be tied to VCC through a pullup resistor. Active-low control output for an external P-channel MOSFET to provide extra power to the 1-Wire line, e.g., for use with 1-Wire devices that require a higher current temporarily to operate. IC Address Inputs. Must be tied to VCC or GND. These inputs determine the IC slave address of the device (see Figure 9). 4 of 21 DS2482-100: Single-Channel 1-Wire Master Figure 1. Block Diagram DS2482-100 Config Register T-Time OSC SDA SCL IC Interface Controller I/O Controller Line XCVR IO PCTLZ AD0 AD1 Status Register Read Data Register DETAILED DESCRIPTION The DS2482-100 is a self-timed 1-Wire master, which supports advanced 1-Wire waveform features including standard and Overdrive speeds, active pullup, strong pullup for power delivery, and presence-pulse masking. Once supplied with command and data, the I/O controller of the DS2482 performs time-critical 1-Wire communication functions such as reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search, without requiring interaction with the host processor. The host obtains feedback (completion of a 1-Wire function, presence pulse, 1-Wire short, search direction taken) through the Status register and data through the Read Data register. The DS2482 communicates with a host processor through its IC bus interface in standard mode or in fast mode. The logic state of two address pins determines the IC slave address of the DS2482, allowing up to four devices operating on the same bus segment without requiring a hub. DEVICE REGISTERS The DS2482 has three registers that the IC host can read: Configuration, Status, and Read Data. These registers are addressed by a read pointer. The position of the read pointer, i.e., the register that the host reads in a subsequent read access, is defined by the instruction that the has DS2482 executed last. The host has read and write access to the Configuration register to enable certain 1-Wire features. Configuration Register The DS2482 supports allows four 1-Wire features that are enabled or selected through the Configuration register. These features are: Active Pullup (APU) Presence Pulse Masking (PPM) Strong Pullup (SPU) 1-Wire Speed (1WS) These features can be selected in any combination. While APU, PPM, and 1WS maintain their state, SPU returns to its inactive state as soon as the strong pullup has ended. Configuration Register Bit Assignment bit 7 1WS bit 6 SPU bit 5 PPM bit 4 APU bit 3 1WS bit 2 SPU bit 1 PPM bit 0 APU After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration register reads 00h. When writing to the Configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h. 5 of 21 DS2482-100: Single-Channel 1-Wire Master Active Pullup (APU) The APU bit controls whether an active pullup (controlled slew-rate transistor) or a passive pullup (RWPU resistor) is used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor mode). Active Pullup should be selected if the 1-Wire line has a substantial length (several 10m) or if there is a large number (~20 or more) of devices connected to a 1-Wire line. The active pullup does not apply to the rising edge of a presence pulse or a recovery after a short on the 1-Wire line. The circuit that controls rising edges (Figure 2) operates as follows: At t1 the pulldown (from DS2482 or 1-Wire slave) ends. From this point on the 1-Wire bus is pulled high through RWPU internal to the DS2482. VCC and the capacitive load of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive pullup continues, as represented by the solid line. With active pullup enabled (APU = 1), when at t2 the voltage has reached a level between VIL1max and VIH1min, the DS2482 actively pulls the 1-Wire line high applying a controlled slew rate, as represented by the dashed line. The active pullup continues until tAPUOT is expired at t3. From that time on the resistive pullup will continue. Figure 2. Rising Edge Pullup VCC VIH1MIN APU = 1 APU = 0 VIL1MAX 0V 1-Wire bus is discharged tAPUOT t1 t2 t3 Presence-Pulse Masking (PPM) The PPM bit controls whether the DS2482 masks the leading edge (falling) of presence pulses. When PPM = 0, masking is disabled. Presence pulse masking applies only to standard 1-Wire speed (1WS = 0); this bit has no function if 1WS = 1 (Overdrive speed). Presence-Pulse Masking can improve the performance of large 1-Wire networks since it prevents the fast falling edge of a presence pulse generated by a 1-Wire slave device from propagating through the network and getting reflected. Reflections can cause glitches in the network that in turn can cause slave devices to lose synchronization with the 1-Wire master. Figure 3 shows the timing references for the Presence-Pulse Masking. If enabled (PPM = 1), the DS2482 begins pulling the 1-Wire line low at tPPM1 after the reset low time tRSTL is expired. The pulldown ends at tPPM2, at which a 1-Wire slave, if present, is pulling the 1-Wire line low. The falling edge of the presence-pulse mask is slew-rate controlled. Figure 3. Presence-Pulse Masking RESET PULSE VCC APU controlled edge Resistive pull-up 0V tRSTL tPPM1 tPPM2 tRSTH DS2482 Pull-down 1-W Slave Pull-down PRESENCE PULSE Pull-up DS2482 pull-down with PPM = 1; Standard speed only 6 of 21 DS2482-100: Single-Channel 1-Wire Master Strong Pullup (SPU) The SPU bit controls whether the DS2482 will apply a low impedance pullup to VCC on the 1-Wire line after the last bit of either a 1-Wire Write Byte command or after a 1-Wire Single Bit command has completed. The strong pullup feature is commonly used with 1-Wire EEPROM devices when copying scratchpad data to the main memory or when performing a SHA-1 computation, and with parasitically powered temperature sensors or A-to-D converters. The respective device data sheets specify the location in the communications protocol after which the strong pullup should be applied. The SPU bit in the Configuration register of the DS2482 must be set immediately prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power. If SPU is 1, the DS2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts, regardless of the APU bit setting. However, in contrast to setting APU = 1 for active pullup, the low-impedance pullup does not end after tAPUOT is expired. Instead, as shown in Figure 4, the low-impedance pullup remains active until either the next 1-Wire communication command is issued (the typical case), the Configuration register is written to with the SPU bit being 0, or the Device Reset command is issued. The PCTLZ control output is active low for the entire duration of the low-impedance pullup, enabling an external p-channel MOSFET to supply additional power to the 1-Wire line. PCTLZ remains inactive (high) at all other time slots that do not use the strong pullup feature. Additionally, when the pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup does not change the state of the APU bit in the Configuration register. Figure 4. Low-Impedance Pullup Timing Vcc Last bit of 1-Wire Write Byte or 1-Wire Single Bit Function Write 1 Edges with active pull-up Write 0 0V tSLOT Pull-up DS2482 Pull-down Next Time Slot DS2482 Low Impedance Pull-up 1-Wire Speed (1WS) The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482. All 1-Wire slave devices support standard speed (1WS = 0), where the transfer of a single bit (tSLOT in Figure 4) is completed within 65s. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from standard to Overdrive speed, a 1-Wire device needs to receive an Overdrive Skip ROM or Overdrive Match ROM command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device has received the speed-changing command code. The DS2482 must take part in this speed change to stay synchronized. This is accomplished by writing to the Configuration register with the 1WS bit being 1 immediately after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration register with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482 and any 1-Wire devices on the active 1-Wire line back to standard speed. Status Register The read-only Status register is the general means for the DS2482 to report bit-type data from the 1-Wire side, 1-Wire busy status and its own reset status to the host processor. All 1-Wire communication commands and the Device Reset command position the read pointer at the Status register for the host processor to read with minimal protocol overhead. Status information is updated during the execution of certain commands only. Details are given in the description of the various status bits below. Status Register Bit Assignment bit 7 DIR bit 6 TSB bit 5 SBR bit 4 RST bit 3 LL bit 2 SD bit 1 PPD bit 0 1WB 7 of 21 DS2482-100: Single-Channel 1-Wire Master 1-Wire Busy (1WB) The 1WB bit reports to the host processor whether the 1-Wire line is busy. During 1-Wire communication 1WB is 1; once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and for how long it remains at 1 are found in the Function Commands section. Presence-Pulse Detect (PPD) The PPD bit is updated with every 1-Wire Reset command. If the DS2482 detects a presence pulse from a 1-Wire device at tMSP during the Presence Detect cycle, the PPD bit will be set to 1. This bit returns to its default 0 if there is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command. Short Detected (SD) The SD bit is updated with every 1-Wire Reset command. If the DS2482 detects a logic 0 on the 1-Wire line at tSI during the Presence Detect cycle, the SD bit is set to 1. This bit returns to its default 0 with a subsequent 1-Wire Reset command provided that the short has been removed. If SD is 1, PPD is 0. The DS2482 cannot distinguish between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a DS2404/DS1994 is used in the application, the interrupt function must be disabled. The interrupt signaling is explained in the respective device data sheets. Logic Level (LL) The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire communication. The 1-Wire line is sampled for this purpose every time the Status register is read. The sampling and updating of the LL bit takes place when the host processor has addressed the DS2482 in read mode (during the acknowledge cycle), provided that the Read Pointer is positioned at the Status register. Device Reset (RST) If the RST bit is 1, the DS2482 has performed an internal reset cycle, either caused by a power-on reset or from executing the Device Reset command. The RST bit is cleared automatically when the DS2482 executes a Write Configuration command to restore the selection of the desired 1-Wire features. Single Bit Result (SBR) The SBR bit reports the logic state of the active 1-Wire line sampled at tMSR of a 1-Wire Single Bit command or the first bit of a 1-Wire Triplet command. The power-on default of SBR is 0. If the 1-Wire Single Bit command sends a 0-bit, SBR should be 0. With a 1-Wire Triplet command, SBR could be 0 as well as 1, depending on the response of the 1-Wire devices connected. The same result applies to a 1-Wire Single Bit command that sends a 1-bit. Triplet Second Bit (TSB) The TSB bit reports the logic state of the active 1-Wire line sampled at tMSR of the second bit of a 1-Wire Triplet command. The power-on default of TSB is 0. This bit is updated only with a 1-Wire Triplet command and has no function with other commands. Branch Direction taken (DIR) Whenever a 1-Write Triplet command is executed, this bit reports to the host processor the search direction that rd was chosen by the 3 bit of the triplet. The power-on default of DIR is 0. This bit is updated only with a 1-Wire Triplet command and has no function with other commands. For additional information see the description of the 1-Wire Triplet command and the Dallas Application Note 187, "1-Wire Search Algorithm". 8 of 21 DS2482-100: Single-Channel 1-Wire Master FUNCTION COMMANDS The DS2482 understands eight function commands, which fall into four categories: device control, IC communication, 1-Wire set-up and 1-Wire communication. The feedback path to the host is controlled by a read pointer, which is set automatically by each function command for the host to efficiently access relevant information. The host processor sends these commands and applicable parameters as strings of one or two bytes using the IC interface. The IC protocol requires that each byte be acknowledged by the receiving party to confirm acceptance or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the communication. Details of the IC protocol including acknowledge are found in the IC interface description of this document. Device Reset Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected F0h None Performs a global reset of device state machine logic. Terminates any ongoing 1-Wire communication. Device initialization after power-up; re-initialization (reset) as desired. None (can be executed at any time) None Maximum 525ns, counted from falling SCL edge of the command code acknowledge bit. Ends maximum 262.5ns after the falling SCL edge of the command code acknowledge bit. Status register (for busy polling) RST set to 1, 1WB, PPD, SD, SBR, TSB, DIR set to 0 1WS, APU, PPM, SPU set to 0 Set Read Pointer Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Valid Pointer Codes Register Selection Status Register Read Data Register Configuration Register Code F0h E1h C3h E1h Pointer Code Sets the Read Pointer to the specified register. Overwrites the read pointer position of any 1-Wire communication command in progress. To prepare reading the result from a 1-Wire Byte command; random read access of registers. None (can be executed at any time) If the pointer code is not valid, the pointer code is not acknowledged and the command is ignored. None; the read pointer is updated on the rising SCL edge of the pointer code acknowledge bit. Not affected As specified by the pointer code None None 9 of 21 DS2482-100: Single-Channel 1-Wire Master Write Configuration Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected D2h Configuration Byte Writes a new configuration byte. The new settings take effect immediately. NOTE: When writing to the Configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h. Defining the features for subsequent 1-Wire communication. 1-Wire activity must have ended before the DS2482 can process this command. Command code and parameter are not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored. None; the Configuration register is updated on the rising SCL edge of the configuration byte acknowledge bit. None Configuration register (to verify write) RST set to 0 1WS, SPU, PPM, APU updated 1-Wire Reset Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected B4h None Generates a 1-Wire Reset/Presence Detect cycle (Figure 5) at the 1-Wire line. The state of the 1-Wire line is sampled at tSI and tMSP and the result is reported to the host processor through the Status register, bits PPD and SD. To initiate or end any 1-Wire communication sequence. 1-Wire activity must have ended before the DS2482 can process this command. Command code is not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored. tRSTL + tRSTH + maximum 262.5ns, counted from the falling SCL edge of the command code acknowledge bit. Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit. Status register (for busy polling) 1WB (set to 1 for tRSTL + tRSTH), PPD is updated at tRSTL + tMSP, SD is updated at tRSTL + tSI 1WS, PPM, APU apply 10 of 21 DS2482-100: Single-Channel 1-Wire Master Figure 5. 1-Wire Reset/Presence Detect Cycle RESET PULSE VCC VIH1 VIL1 0V PRESENCE/SHORT DETECT tSI tMSP tF1 tRSTL Pull-up DS2482 pull-down tRSTH 1-W Slave pull down For presence pulse masking and pull-up details see Figure 3. 1-Wire Single Bit Command Code Command Parameter Description 87h Bit Byte Generates a single 1-Wire time slot with a bit value `V' as specified by the bit byte at the 1-Wire line. A `V' value of 0b generates a write-zero time slot (Figure 6), a value of 1b generates a write-one slot, which also functions as a read-data time slot (Figure 7). In either case the logic level at the 1-Wire line is tested at tMSR and SBR is updated. To perform single bit writes or reads at the 1-Wire line when single bit communication is necessary (the exception). 1-Wire activity must have ended before the DS2482 can process this command. Command code and bit byte are not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored. tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MS bit) of the bit byte. Begins maximum 262.5ns after the falling SCL edge of the MS bit of the bit byte. Status register (for busy polling and data reading) 1WB (set to 1 for tSLOT) SBR is updated at tMSR DIR (may change its state) 1WS, APU, SPU apply Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Bit Allocation in the Bit Byte bit 7 bit 6 V x x = don't care bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x 11 of 21 DS2482-100: Single-Channel 1-Wire Master Figure 6. Write-0 Time Slot Vcc VIH1 VIL1 0V tF1 Pull-up (see Fig. 2) tSLOT DS2482 pull-down tREC0 tW0L tMSR Figure 7. Write-1 and Read-Data Time Slot Vcc VIH1 VIL1 0V tF1 tSLOT Pull-up (see Fig. 2) DS2482 pull-down 1-W Slave pull-down tW1L tMSR NOTE on Figure 7: Depending on its internal state, a 1-Wire slave device transmits data to its master (e.g., the DS2482). When responding with a 0, a 1-Wire slave starts pulling the line low during tW1L; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, a 1-Wire slave does not hold the line low at all, and the voltage starts rising as soon as tW1L is over. 1-Wire device data sheets use the term tRL instead of tW1L to describe a Read-Data Time Slot. Technically, tRL and tW1L have identical specifications and cannot be distinguished from each other. 1-Wire Write Byte Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration A5h Data Byte Writes single data byte to the 1-Wire line. To write commands or data to the 1-Wire line; equivalent to executing eight 1-Wire Single Bit commands, but faster due to less IC traffic. 1-Wire activity must have ended before the DS2482 can process this command. Command code and data byte are not acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. 8 x tSLOT + maximum 262.5ns, counted from falling edge of the last bit (LS bit) of the data byte. Begins maximum 262.5ns after falling SCL edge of the LS bit of the data byte (i.e., before the data byte acknowledge). NOTE: The bit order on the IC bus and the 1-Wire line is different. (1-Wire: LS-bit first; IC: MS-bit first) Therefore, 1-Wire activity cannot begin before the DS2482 has received the full data byte. Status register (for busy polling) 1WB (set to 1 for 8 x tSLOT) 1WS, SPU, APU apply 12 of 21 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected DS2482-100: Single-Channel 1-Wire Master 1-Wire Read Byte Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected 96h None Generates eight read-data time slots on the 1-Wire line and stores result in the Read Data register. To read data from the 1-Wire line; equivalent to executing eight 1-Wire Single Bit commands with V = 1 (write-1 time slot), but faster due to less IC traffic. 1-Wire activity must have ended before the DS2482 can process this command. Command code is not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored. 8 x tSLOT + maximum 262.5ns, counted from the falling SCL edge of the command code acknowledge bit. Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit. Status register (for busy polling) NOTE: To read the data byte received from the 1-Wire line, issue the Set Read Pointer command and select the Read Data register. Then access the DS2482 in read mode. 1WB (set to 1 for 8 x tSLOT) 1WS, APU apply 1-Wire Triplet Command Code Command Parameter 78h Direction Byte Generates three times slots, two read time slots and one write time slot at the 1-Wire line. The type of write time slot depends on the result of the read time slots and the direction byte. The direction byte determines the type of write time slot if both read time slots are 0 (a typical case). In this case the DS2482 generates a write 1time slot if V = 1 and a write-0 time slot if V = 0. If the read time slots are 0 and 1, there follows a write-0 time slot. If the read time slots are 1 and 0, there follows a write-1 time slot. If the read time slots are both 1 (error case), the subsequent write time slot is a write 1. To perform a 1-Wire Search ROM sequence; a full sequence requires this command to be executed 64 times to identify and address one device. 1-Wire activity must have ended before the DS2482 can process this command. Command code and direction byte is not acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. 3 x tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MS bit) of the direction byte. Begins maximum 262.5ns after the falling SCL edge of the MS bit of the direction byte. Status register (for busy polling) 1WB (set to 1 for 3 x tSLOT) SBR is updated at the first tMSR TSB and DIR are updated at the second tMSR (i. e., at tSLOT + tMSR) 1WS, APU apply Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Bit Allocation in the Direction Byte bit 7 V bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x x = don't care 13 of 21 DS2482-100: Single-Channel 1-Wire Master IC INTERFACE General Characteristics The IC bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the IC-bus can be transferred at rates of up to 100kbps in the standard mode, up to 400kbps in the fast mode. The DS2482 works in both modes. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the communication is called a "master." The devices that are controlled by the master are "slaves." To be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls the bus access, generates the START and STOP conditions, and determines the number of data bytes transferred between START and STOP (Figure 8). Data is transferred in bytes with the most significant bit being transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave. Figure 8. IC Protocol Overview MS-bit SDA Slave Address Acknowledgment from Receiver Repeated if more bytes are transferred R/W ACK bit ACK bit SCL Idle START Condition 1 2 6 7 8 9 ACK 1 2 8 9 ACK STOP Condition Repeated START Condition Slave Address The slave address to which the DS2482 responds is shown in Figure 9. The logic states at the address pins AD0 and AD1 determine the value of the address bits A0 and A1. The address pins allow the device to respond to one of four possible slave addresses. The slave address is part of the slave-address/control byte. The last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data flows from master to slave (write access); when set to a 1, data flows from slave to master (read access). Figure 9. DS2482 Slave Address 7-Bit Slave Address A6 0 A5 0 A4 1 A3 1 A2 0 A1 A0 AD1 AD0 R/W Most Significant Bit AD1, AD0 Pin States Determines Read or Write 14 of 21 DS2482-100: Single-Channel 1-Wire Master IC Definitions The following terminology is commonly used to describe IC data transfers. The timing references are defined in Figure 10. Figure 10. IC Timing Diagram SDA tBUF tLOW tF tHD:STA tSP SCL tHD:STA tR tHD:DAT STOP START tHIGH tSU:DAT Repeated START tSU:STA Spike Suppression tSU:STO NOTE: Timing is referenced to VILMAX and VIHMIN. Bus Idle or Not Busy: Both, SDA and SCL, are inactive and in their logic HIGH states. START Condition: To initiate communication with a slave, the master has to generate a START condition. A START condition is defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. STOP Condition: To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as a change in state of SDA from LOW to HIGH while SCL remains HIGH. Repeated START Condition: Repeated starts are commonly used for read accesses to select a specific data source or address to read from. The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal START condition, but without leaving the bus idle after a STOP condition. Data Valid: With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 10). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL. When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum tSU:DAT + tR in Figure 10) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master generates all SCL clock pulses, including those needed to read from a slave. Acknowledge: Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL). Not Acknowledged by Slave: A slave device may be unable to receive or transmit data, e.g., because it is busy performing some real-time function. In this case the slave device does not acknowledge its slave address and leaves the SDA line HIGH. 15 of 21 DS2482-100: Single-Channel 1-Wire Master A slave device that is ready to communicate will acknowledge at least its slave address. However, some time later the slave may refuse to accept data, e.g., because of an invalid command code or parameter. In this case the slave device does not acknowledge any of the bytes that it refuses and leaves SDA HIGH. In either case, after a slave has failed to acknowledge, the master first needs to generate a repeated START condition or a STOP condition followed by a START condition to begin a new data transfer. Not Acknowledged by Master: At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the master does not acknowledge the last byte that it has received from the slave. In response, the slave releases SDA, allowing the master to generate the STOP condition. Writing to the DS2482 To write to the DS2482, the master must access the device in write mode, i.e., the slave address must be sent with the direction bit set to 0. The next byte to be sent is a command code, which, depending on the command, may be followed by a command parameter. The DS2482 acknowledges valid command codes and expected/valid command parameters. Additional bytes or invalid command parameters are never acknowledged. Reading from the DS2482 To read from the DS2482, the master must access the device in read mode, i.e., the slave address must be sent with the direction bit set to 1. The read pointer determines the register that the master will read from. The master may continue reading the same register over and over again, without having to re-address the device, e.g., to watch the 1WB changing from 1 to 0. To read from a different register, the master must issue the Set Read Pointer command and then access the DS2482 again in read mode. IC Communication--Legend SYMBOL S AD, 0 AD, 1 Sr P A A\ (Idle) Data Direction Codes Master-to-Slave Slave-to-Master 16 of 21 DS2482-100: Single-Channel 1-Wire Master IC Communication Examples Device Reset, e.g., After Power-Up S AD,0 A DRST A Sr AD,1 A This example includes an optional read access to verify the success of the command. Write Configuration, e.g., Before Starting 1-Wire Activity Power-Up Case A: 1-Wire Idle (1WB = 0) S AD,0 A WCFG A A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. Set Read Pointer, e.g., to Read from Another Register Case A: Valid Read Pointer Code S AD,0 A SRP A C3h A P C3h is the valid read pointer code for the Configuration register. Case B: Invalid Read Pointer Code S AD,0 A SRP A E5h A\ P E5h is an invalid read pointer code. 1-Wire Reset, e.g., to Begin or End 1-Wire Communication Case A: 1-Wire Idle (1WB = 0), No Busy Polling to Read the Result S AD,0 A 1WRS A P (Idle) S AD,1 A Repeat until the 1WB bit has changed to 0. Case C: 1-Wire Busy (1WB = 1) S AD,0 A 1WRS A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 17 of 21 DS2482-100: Single-Channel 1-Wire Master 1-Wire Write Byte, e.g., to Send a Command Code to the 1-Wire Line Case A: 1-Wire idle (1WB = 0), No Busy Polling S AD,0 A 1WWB A 33h A P (Idle) 33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to complete. There is no data read back from the 1-Wire line with this command. Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed. S AD,0 A 1WWB A Sr 33h A AD,1 A When 1WB has changed from 1 to 0, the 1-Wire Write Byte command is completed. Case C: 1-Wire Busy (1WB = 1) S AD,0 A 1WWB A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 1-Wire Read Byte, e.g., to Read a Byte from the 1-Wire Line Case A: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer After Idle Time S S AD,0 AD,0 A A 1WRB SRP A A P E1h (Idle) A Sr AD,1 A The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the Read Data register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line. Case B: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer Before Idle Time S AD,0 A 1WRB A Sr (Idle) AD,0 S A AD,1 A SRP A A\ E1h P A P The read pointer is set to the Read Data register (code E1h) while the 1-Wire Read Byte command is still in progress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was obtained from the 1-Wire line. Case C: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed Repeat until the 1WB S AD,0 A 1WRB A bit has changed to 0. Sr Sr AD,0 A SRP A E1h AD,1 A A Sr Poll the Status register until the 1WB bit has changed from 1 to 0. Then set the read pointer to the Read Data register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line. Case D: 1-Wire Busy (1WB = 1) S AD,0 A 1WRB A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 18 of 21 DS2482-100: Single-Channel 1-Wire Master 1-Wire Single Bit, e.g., to Generate a Single Time Slot on the 1-Wire Line Case A: 1-Wire Idle (1WB = 0), No Busy Polling S AD,0 A 1WSB A AD,1 The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result from the 1-Wire single-bit command. Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed S AD,0 A 1WSB A AD,1 When 1WB has changed from 1 to 0, the Status register holds the valid result of the 1-Wire Single Bit command. Case C: 1-Wire Busy (1WB = 1) S AD,0 A 1WSB A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 1-Wire Triplet, e.g., to Perform a Search ROM Function on the 1-Wire Line Case A: 1-Wire Idle (1WB = 0), No Busy Polling S AD,0 A 1WT A AD,1 The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result from the 1-Wire Triplet command. Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed S AD,0 A 1WT A AD,1 When 1WB has changed from 1 to 0, the Status register holds the valid result of the 1-Wire Triplet command. Case C: 1-Wire Busy (1WB = 1) S AD,0 A 1WT A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 19 of 21 DS2482-100: Single-Channel 1-Wire Master Figure 11. Application Schematic VCC *RP (IC port) SDA SCL PCTLZ Current Limiting Resistor C DS2482-100 AD0 AD1 *Rt 1-Wire line 1-Wire Device #1 (with special power requirements) IO VCC SDA SCL PCTLZ * Rt Line termination resistor, typically 100W RP IC pull-up resistor, see Application Information for RP sizing. DS2482-100 VCC AD0 AD1 *Rt IO 1-Wire line 1-Wire Device #2 Application Information SDA and SCL Pullup Resistors SDA is an open-drain output on the DS2482 that requires a pullup resistor to realize high logic levels. Because the DS2482 uses SCL only as input (no clock stretching) the master may drive SCL either through an opendrain/collector output with a pullup resistor or a push-pull output. Pullup Resistor RP Sizing According to the IC specification, a slave device must be able to sink at least 3mA at a VOL of 0.4V. This DC condition determines the minimum value of the pullup resistor: Rpmin = (VCC - 0.4V)/3mA. With an operating voltage of 5.5V, the minimum value for the pullup resistor is 1.7kW. The "Minimum RP" line in Figure 12 shows how the minimum pullup resistor changes with the operating voltage. For IC systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum bus capacitance Cb is 400 pF. The maximum rise time at standard speed must not exceed 1000ns and 300ns at fast speed. Assuming maximum rise time, the maximum resistor value at any given capacitance Cb is calculated as: Rpmaxs = 1000ns/(Cb*ln(7/3)) (standard speed) and Rpmaxf = 300ns/(Cb*ln(7/3)) (fast speed). For a bus capacitance of 400pF the maximum pullup resistor values are 2.95kW at standard speed and 885W at fast speed. A value between of 1.7kW and 2.95kW meets all requirements at standard speed. 20 of 21 DS2482-100: Single-Channel 1-Wire Master Since a 885W pullup resistor, as would be required to meet the rise time specification at fast speed and 400pF bus capacitance, is lower than Rpmin at 5.5V, a different approach is necessary. The "Max. Load..." line in Figure 12 is generated by first calculating the minimum pullup resistor at any given operating voltage ("Minimum Rp" line) and then calculating the respective bus capacitance that yields a rise time of 300ns. Only for pullup voltages of 3V and lower can the maximum permissible bus capacitance of 400pF be maintained. A reduced bus capacitance of 300pF is acceptable for pullup voltages of 4V and lower. For fast speed operation at any pullup voltage, the bus capacitance must not exceed 200pF. The corresponding pullup resistor value at the voltage is indicated by the "Minimum Rp" line. Figure 12. IC Fast Speed Pullup Resistor Selection Chart "Minimum Rp" 2000 Minimum Rp (Ohms) Max. Load at Min. Rp fast mode 500 400 300 200 100 0 Load (pF) 1600 1200 800 400 0 1 2 3 Pull-up Voltage 4 5 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) 21 of 21 |
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